Comparators are useful in a variety of applications where one wishes to obtain a digital representation of the relative magnitudes of two (or more) analog input signals. In certain applications it is desirable that the comparator be of relatively simple construction and include some form of drift compensation (e.g., automatic zeroing). An example of such an application is in so-called "flash" analog to digital converters which may employ as many as 2 exp(N)-1 comparators where N equals the number of bits in the converted digital signal. Eight-bit direct ("flash") converters, for example, may require as many as 255 comparators. This large number of comparators, as a practical matter, precludes use of complex differential amplifier configurations.
A comparator of relatively simple construction and which features drift compensation is described by Davis in the commonly assigned U.S. Pat. No. 3,657,563 entitled AC COUPLED COMPARATOR AND A/D CONVERTER which issued Apr. 18, 1972. An embodiment of an analog to digital converter shown by Davis includes a comparator in which input signals to be compared are AC coupled to a three stage (inverting) MOS transistor amplifier. Automatic zeroing is achieved by applying a first of two input signals to be compared to the amplifier input via a coupling capacitor while shorting the amplifier input/output terminals. The short circuit causes the amplifier to self-bias itself to an operating region of maximum gain and linearity and causes the input coupling capacitor to store an offset or compensating voltage equal to the difference of the input signal voltage and the amplifier self-bias voltage.
After automatic zeroing, the short circuit is removed and the second input signal is substituted for the first input signal. Since the amplifier offset was stored in the coupling capacitor during the auto-zero interval and the same capacitor is used during the comparison interval for coupling the second input signal, the amplifier offset is effectively cancelled and the amplifier output signal polarity thus provides an accurate indication of the relative magnitudes of the two input signals.
In the embodiment of the Davis comparator discussed above, the amplifier was implemented by connecting three non-complementary MOS transistor amplifier stages in cascade. Comparators of similar construction have been described using fewer amplifier stages and employing complementary MOS (CMOS hereafter) inverter stages for amplification. Examples of comparators employing dynamically self-biased CMOS inverter amplifier stages are described by Gregorian et al. in the text book ANALOG MOS INTEGRATED CIRCUITS FOR SIGNAL PROCESSING, Section 6.3 "MOS Comparators" pp. 425-437, published by John Wiley & Sons in 1986.
In examples of CMOS comparators described by Gregorian et al., input signals to be compared are alternately applied by a coupling capacitor to the input node of a CMOS inverter. The inverter includes a switch connected between the inverter input and output nodes and power terminals connected to sources of positive (Vdd) and negative (Vss) supply voltage. During auto zeroing, a reference (ground) level signal is applied to the coupling capacitor and the amplifier feedback switch is closed thereby self-biasing the amplifier and charging the capacitor to a voltage equal to the difference between the reference value (ground) and the amplifier self-bias operating point voltage. In the compare mode the input voltage to be compared (against ground level) is applied to the capacitor and the feedback switch is opened thus enabling the CMOS inverter to amplify (sense) the difference between the input voltages. As in the Davis arrangement, storage of the amplifier self-bias voltage in the coupling capacitor during the auto-zero and compare phases effectively corrects for amplifier offset and drift effects (assuming the drift to be negligible during the comparator cycle time).